Semiconductor component manufacturers typically include structures for protecting their devices against failure caused by large transient electrical stimuli. When the stimulus is an electrostatic discharge (“ESD”) event, manufacturers generally incorporate protection structures that account for failure mechanisms attributed to the Human Body Model (“HBM”) and to the Charged Device Model (“CDM”). The Human Body Model simulates electrostatic discharge from a human body to a semiconductor device that is sensitive to the discharge event. Here, charge accumulated on the human body discharges to the semiconductor device. The Charged Device Model simulates the discharge of charge accumulated on the semiconductor device itself during the assembly process. When these charged devices contact metal objects, a discharge event occurs which is short in duration accompanied by peak currents capable of exceeding ten amperes.
To protect against these events, semiconductor component manufacturers incorporate ESD protection structures into their components. They are coupled to input and output (“I/O”) pads of the semiconductor devices to prevent device failure due to positive and negative voltage excursions that may appear on the I/O pads. To provide maximal ESD protection, it is desirable to increase the discharge path for ESD induced current by making the ESD protection structures large. However, large ESD protection structures occupy large areas on the semiconductor substrate, which increases the costs associated with manufacturing the semiconductor component. In addition, making the ESD protection structures large increases the capacitance associated with the input and output pads to which they are coupled. In high frequency applications, increasing the capacitance of the ESD protection structure increases the Resistance-Capacitance (“RC”) time constant of the pin coupled to the bond pad, which makes the devices unacceptably slow.
Accordingly, it would be advantageous to have an ESD protection structure with reduced capacitance during normal operation and a method for lowering the capacitance of the ESD protection structure. It would be of further advantage for the method and ESD protection structure to be cost efficient.